rx_cic
2021.04.08.14:14:21
Datasheet
Overview
Memory Map
cic_ii_0
altera_cic_ii v18.1
Parameters
design_env
NATIVE
selected_device_family
CYCLONEIVE
FILTER_TYPE
decimator
STAGES
6
D_DELAY
1
VRC_EN
1
RCF_FIX
640
RCF_LB
160
RCF_UB
1280
RCF_MIN
160
RCF_MAX
1280
INTERFACES
1
CH_PER_INT
1
IN_WIDTH
31
CLK_EN_PORT
true
ROUND_TYPE
CONV_ROUND
REQ_OUT_WIDTH
32
OUT_WIDTH
32
INT_USE_MEM
false
INT_MEM
auto
REQ_INT_MEM
logic_element
DIF_USE_MEM
false
DIF_MEM
auto
REQ_DIF_MEM
logic_element
REQ_PIPELINE
0
PIPELINING
0
C_STAGE_0_WIDTH
93
I_STAGE_0_WIDTH
93
C_STAGE_1_WIDTH
93
I_STAGE_1_WIDTH
93
C_STAGE_2_WIDTH
93
I_STAGE_2_WIDTH
93
C_STAGE_3_WIDTH
93
I_STAGE_3_WIDTH
93
C_STAGE_4_WIDTH
93
I_STAGE_4_WIDTH
93
C_STAGE_5_WIDTH
93
I_STAGE_5_WIDTH
93
C_STAGE_6_WIDTH
93
I_STAGE_6_WIDTH
93
C_STAGE_7_WIDTH
93
I_STAGE_7_WIDTH
93
C_STAGE_8_WIDTH
93
I_STAGE_8_WIDTH
93
C_STAGE_9_WIDTH
93
I_STAGE_9_WIDTH
93
C_STAGE_10_WIDTH
93
I_STAGE_10_WIDTH
93
C_STAGE_11_WIDTH
93
I_STAGE_11_WIDTH
93
MAX_I_STAGE_WIDTH
93
MAX_C_STAGE_WIDTH
93
hyper_opt_select
0
hyper_opt
0
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0,01 seconds
rendering took 0,03 seconds