tx_cic
2020.12.05.17:16:14
Datasheet
Overview
Memory Map
cic_ii_0
altera_cic_ii v18.1
Parameters
design_env
NATIVE
selected_device_family
CYCLONEIVE
FILTER_TYPE
interpolator
STAGES
4
D_DELAY
1
VRC_EN
0
RCF_FIX
3920
RCF_LB
8
RCF_UB
21
RCF_MIN
3920
RCF_MAX
3920
INTERFACES
1
CH_PER_INT
1
IN_WIDTH
16
CLK_EN_PORT
false
ROUND_TYPE
CONV_ROUND
REQ_OUT_WIDTH
14
OUT_WIDTH
14
INT_USE_MEM
false
INT_MEM
auto
REQ_INT_MEM
logic_element
DIF_USE_MEM
false
DIF_MEM
auto
REQ_DIF_MEM
logic_element
REQ_PIPELINE
0
PIPELINING
0
C_STAGE_0_WIDTH
52
I_STAGE_0_WIDTH
52
C_STAGE_1_WIDTH
52
I_STAGE_1_WIDTH
52
C_STAGE_2_WIDTH
52
I_STAGE_2_WIDTH
52
C_STAGE_3_WIDTH
52
I_STAGE_3_WIDTH
52
C_STAGE_4_WIDTH
52
I_STAGE_4_WIDTH
52
C_STAGE_5_WIDTH
52
I_STAGE_5_WIDTH
52
C_STAGE_6_WIDTH
52
I_STAGE_6_WIDTH
52
C_STAGE_7_WIDTH
52
I_STAGE_7_WIDTH
52
C_STAGE_8_WIDTH
52
I_STAGE_8_WIDTH
52
C_STAGE_9_WIDTH
52
I_STAGE_9_WIDTH
52
C_STAGE_10_WIDTH
52
I_STAGE_10_WIDTH
52
C_STAGE_11_WIDTH
52
I_STAGE_11_WIDTH
52
MAX_I_STAGE_WIDTH
52
MAX_C_STAGE_WIDTH
52
hyper_opt_select
0
hyper_opt
0
deviceFamily
UNKNOWN
generateLegacySim
false
Software Assignments
(none)
generation took 0,01 seconds
rendering took 0,02 seconds