Title: DDC Module2
Post by: SP9BSL on 12. August 2020, 16:54:20
Hi,
looks like all the world goes into the digital domain (and BGA of course) ...
http://www.cqham.ru/forum/showthread.php?42117-DDC-Module-2-%E2-%F2%F0%E0%ED%F1%E8%E2%E5%F0%E0%F5-M0NKA-UHDSDR-OVI-40-Sparrow-%E8-%E4%F0&p=1761399&viewfull=1#post1761399 (http://www.cqham.ru/forum/showthread.php?42117-DDC-Module-2-%E2-%F2%F0%E0%ED%F1%E8%E2%E5%F0%E0%F5-M0NKA-UHDSDR-OVI-40-Sparrow-%E8-%E4%F0&p=1761399&viewfull=1#post1761399) |
Title: Re:DDC Module2
Post by: DF8OE on 12. August 2020, 17:09:25
Ja - das ist wirklich spannend. Ich kann fast kein Russisch mehr ich hatte es nur 1/2 Jahr in der Schule und dann wurde unser Lehrer aufgrund politischer Verstimmungen (kalter Krieg...) wieder nach Russland zurückbeordert :'(... Also muss Google helfen.
Wie ich sehe ich auch dieses Board mit dem berüchtigten "Sprint-Layout" gemacht - ist das richtig? Und obwohl da steht "alles offen" konnte ich keine Schematics finden. Odr ist mein Übersetzer fehlerhaft?
vy 73
Andreas |
Title: Re:DDC Module2
Post by: SP9BSL on 12. August 2020, 17:28:19
Yes, it's pity that he doesn't provide the schematics. Looks like he is comfortable developing this way.
Cyclone 10 is fairly new chip, although not a big step in technology compared to Cyclone IV, and really not a big advantage looking at the prices (or clones).
Edit:
It is interesting if the board supports the 6m band because of low maximum ADC sample clock. Also there is lack of low phase noise clock. The chip capacity is too low for two receivers working simultaneously but this is minor issue, the chip can be migrated to higher density easily... |
Title: Re:DDC Module2
Post by: SP9BSL on 13. August 2020, 08:09:51
Hi,
looks like Rolin will have "own" version of UI (the citation from Russian forum):
" And so far everything is complicated with software, I have never coded in C ++, and even under STM32. So far I decided to make my own version of the Sparrow 4 printed circuit board, where the module will be normally installed, the power is normally done and what would be with the batteries inside.
So if there are enthusiastic specialists here who can "trick" over the UHSDR firmware, you can collaborate.
All you need to do is:
1) - disable checking and displaying an error on the screen at startup for SI570, quadrature audio codec and micro thermometer
2) - remake the I2C control function of the quadrature audio code to control the module.
3) - to remake the DSP to work at zero IF."
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Title: Re:DDC Module2
Post by: DF8OE on 13. August 2020, 09:45:42
Yes - that is "Open Source". And there is nothing against it. We will do nothing else when we connect our DUC/DDC to the board.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: SP9BSL on 13. August 2020, 09:58:43
| The boards runs as slave, simply replacing the RX/TX codec (i assume this from the description) - this is different approach to our. So there must be a sync code in FPGA to align two clocks - the FPGA and the Masterclock from STM. I did not dig in the fpga code yet but this must be tricky or there will be audible clicks. |
Title: Re:DDC Module2
Post by: DF8OE on 13. August 2020, 10:17:17
It can work as master or as slave - as I understand the description...
vy 73
Andreas |
Title: Re:DDC Module2
Post by: BO_Andy on 24. August 2020, 17:47:25
Ich würde mich glatt dazu nochma breit schalten lassen 10 PcBs in Gold zu bestellen
LG BO_Andy |
Title: Re:DDC Module2
Post by: BO_Andy on 25. August 2020, 17:26:26
Das gefällt mir denn würde ich auch noch bauen sobald es denn pcb Satz gibt
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Title: Re:DDC Module2
Post by: SP9BSL on 26. August 2020, 06:34:43
Hi,
some remarks looking at all of this - I don't know if David looks here but if you guys have problem with UHSDR - why don't you prepare the FPGA code to be seen as SI570 on I2C by STM? |
Title: Re:DDC Module2
Post by: DF8OE on 26. August 2020, 07:02:36
It would be a nice idea to invite David.
I am not sure (because I never have looked into SI570 driving words) you can reach very low frequencies without change of code. You can go down to a few KHz with DDC/DUC but you cannot with SI570. Preparation of different product identifier in FPGA can make it easy to decide if DDC/DUC is mounted or not.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: SP9BSL on 26. August 2020, 07:09:48
Hi Andreas,
of course, the identification is ready with SParkle (in upcoming pull request), but I use SPI... Also there is control for amplifier/attenuator with callback function - just need to define it in the specyfic hardware code.
Side question caused by lack of schematics, maybe someone knows - is there a JTAG for fpga on the David's pcb? |
Title: Re:DDC Module2
Post by: DF8OE on 26. August 2020, 07:23:51
Yes it is. Board contains so less of parts that you can get most interesting information out of FPGA code (pin names).
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DF8OE on 26. August 2020, 10:22:43
Hi Artur,
but it is a very nice idea to stay compatible. You have to add some more lines and connectory which are not needed for DUC/DDC but can make PCB 100% compatible with a small "WM8731-PCB" ;D
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DF8OE on 04. September 2020, 13:56:12
Hi Artur,
are there some 0R resistors for I2S and I2C so that you can simply switch from mixing concept to DDC/DUC? That would be a great advantage for those who firstly want to use their old mixnig PCBs and then later switch to DDC/DUC without huge soldering scenarios...
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DF8OE on 04. September 2020, 14:49:25
If this is done at both I2S and all three I2S lines: the solution will not work. When WM is published and you add DDC/DUC you short-circuit the outputs of the busses. That MAY work for the inputs - but definitly not for the outputs of WM and module. There may be problems at the inputs, too because of the load will be critical at higher bus frequencies (and DUC/DDC will use higher frequencies). So it would be mandatory to put one 0R resistor in each line to WM which can be removed easily. Module does not need 0R - you can unplug it 8)
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 05:57:06
Hello, people.
I am here and I am ready to answer all the your questions.
I am doing the Sparrow 4 N7DDC Edition and this is first of all my own vision how it should have been a power delivery system of modern HAM transceiver with battaries power.
I have changed pinout for CPU because I will need to change the firmware in any way.
The RF board will have everithing needed to use 4 LiFePo elements, balanse and charger and also MCU-companion, wich will to control of power and to send for DSP-MCU all the meassured parameters from buid-in ADC. So board to board connector has mainly I2C bus to connect them each other.
I don't know exactly, who knows, probably Artur's version would be more interested for other people, I just realise myself in this project and obviously doing what I want to have personally.
I am ready to change the firmware of DDC Module 2 if anyone wants to use it in his own projects.
At this time I have assembled the CPU board and working on firmware.
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Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 05:57:39
Title: Re:DDC Module2
Post by: SP9BSL on 21. September 2020, 07:32:02
Hello David,
welcome to our forum, glad to see you here. Can you present the list of pinout changes for STM?
You mention on cqham.ru you need to change the UHSDR code to zero IF, can you explain why do you need this? |
Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 15:37:09
Hi.
The header with the pinout you can find here
I need to see the filter on the center of panorama because I can do this using DDC.
Output IQ signals dont have a flicker noise on zero freq unlike signals from audio codec. |
Title: Re:DDC Module2
Post by: DF8OE on 21. September 2020, 15:45:03
But as long as I understand it is impossible to work in FM or AM in zero-IF-mode because you are crossing a division by zero point... Maybe you can get it work in RX but not in TX.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 17:11:00
Hello, Andreas.
All the known SDR progs on PC work in Zero-If and able to work even with variable IF, other words they are able to slide a filter by panorama including zero freq too.
I have noticed one time using QUISK when the 1000kHz domestic AM station is on the center of panorama and the filter tuned on 1000kHz too, the quality of sound is getting very bad. But it is enough to tune the filter even on 1 Herz, the quality is returning back.
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Title: Re:DDC Module2
Post by: DF8OE on 21. September 2020, 17:19:00
FM demodulating code which is used in external software needs so much horse power what is not a problem in a modern PC. If you use zero IF that cannot be realized in an embedded systems same way. To get FM realized we need a "tricky" solution (developed by KA7OEI) which uses much lower horse power but depends on a no-zero crossing signal. So if you switch to zero-if in UHSDR FM is disabled. If you enable it by removing the disabling UHSDR crashes immediately (some ms) after switching to FM because of there are divisions by zero...
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 17:36:39
Is this possible to use IF = 1 Hz or ZeroIF can not to be inside the filter ?
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Title: Re:DDC Module2
Post by: DF8OE on 21. September 2020, 17:58:28
You must shift it so that no wanted products are crossing the zero line. In SSB or CW you can use zero if without problems. In AM you cannot - you will get distortions These are gigantic if the carrier is exactly at zero. If you move it a little bit away the distortions are in the audio signal bandwidth. You can demodulate signal - but it is slightly distorted. In FM you cannot work at zero if in systems which use simplified demodulation routines (like in embedded systems). If your if is too near to zero so that component of your signal are crossing zero you will get gigantic distortions which mostly make from a "Q5 signal" a "Q1 signal". Therefore 6KHz if is a little bit to near to zero. If you are working with low deviation signal may sound ok. But if you increase it your signal bandwidth will cross the zero. So we decided to move to 12KHz which always give a comfortable space between end of signal and zero... But it is not a problem to work in non-zero if mode. You can throw away signal spectrum by cutting the asymmetric spectrum at one side. The only proof is "a symmetrical view". I by myself do not see any sense to do so.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 21. September 2020, 21:46:58
HI, Andreas
I think you are not right.
I remember that time 20 years ago when PowerSDR worked with 12kHz IF, but now all known progs can work on zero freq.
The most important advantage is not only symmetrical view, it is the possibility to tune the filter when the panorama and waterfall are motionless.
I will ask somebody who has a lot experience with this and come back soon. |
Title: Re:DDC Module2
Post by: SP9BSL on 21. September 2020, 21:57:44
The most important advantage is not only symmetrical view, it is the possibility to tune the filter when the panorama and waterfall are motionless.
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Hi David,
this feature is already implemented in the code from very beginning. So far we're not using it because of small display and high overhead for F4 core.
I will ask somebody who has a lot experience with this and come back soon.
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Please do it, there is problem with FM in UHSDR at zero IF, I know because I also have working DDC solution with UHSDR (see SParkle threads). |
Title: Re:DDC Module2
Post by: N7DDC on 22. September 2020, 05:13:44
I have asked George RX9CIM, autor of SDR Tulipan, Visair and Malachit. He confirmed that all the modulation including FM work perfect with zero IF and variable IF.
With sound codec IQ this is impossible.
Tulipan is using STM32F407ZGT6, we have H743 . Should to work !
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Title: Re:DDC Module2
Post by: DF8OE on 22. September 2020, 05:24:01
I by myself do not have the skill to do this. I am happy that I understand the maths in pieces when we are working in time or in frequency domain. But definitely no chance to code this. And I have not yet seen any Open Source project using small horse power as on embedded systems where I can learn how this can be done. Telling "it is possible" does not help. Existing projects where it works but that are Closed Source does not help, too. If you (or anyone) knows someone who can code this and is able to share his knowledge or contribute in a collaboration and versioning system (GitHub): invite her/him. Open Source lives from sharing, contributing and learning from each other.
EDIT:
Because of technical discussion started fast and with many informations I totally forgot - please excuse me:
Welcome to our discussion group David! We want to improve the existing project and extend capabilities - and therefore we are happy that you are present here now.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 22. September 2020, 05:39:38
Hi, Andreas
Thank you
I think you have to try the current DSP code with IQ from DDC. Just remove amplitude and phase balansing, DC removing and try. |
Title: Re:DDC Module2
Post by: DF8OE on 22. September 2020, 08:30:23
That is not the problem and it is crystal clear. Never was any problem! I got it running in RX out-of-the-box. This week I do not have much time to try TX - this will follow next.
What I am talking about is working with zero IF in AM / FM RX and TX without getting signal quality issues. All this is already working flawlessly in 12KHz IF - in narrow band FM with 6KHz, too - but not in zero IF. And I am not able to code zero IF parts. Maybe this a complete different DSP signal path, switching / moving time <--> frequency domain. But as I already told: my DSP knowledges are not big enough to work on this.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: N7DDC on 27. September 2020, 01:45:52
Hello, Artur
Set the amplificator in settings to see the noise with no antenna.
Later I will correct the bitwise shift. |
Title: Re:DDC Module2
Post by: DF8OE on 27. September 2020, 05:48:22
Hi Artur,
at this stage I do not care about any currents and do not measure anything here. There is enough to do at the software integration in a clean way. But I like the currents you posted - very nice for a direct conversion!
vy 73
ANdreas |
Title: Re:DDC Module2
Post by: SP9BSL on 27. September 2020, 07:27:03
| Just set the RX codec gain to 0 and you will see the noise floor. This is not a bug, known behaviour. We will adjust the AGC for spectrum later. |
Title: Re:DDC Module2
Post by: S58J on 28. September 2020, 10:23:22
Hi
I am trying to follow this discussion, strictly from a user perspective (always building a new and BETTER transceivers). Saying that I have to admit that I am not qualified to make comments about the current developments (Sparkle, N7DCC approach, ...). I love to solder and use home transceivers while I am not too much knowledgeable about the "magic behind" each TRX.
I used Google extensively (hi) trying to better understand why adding N7DDC module would made future TRX home made projects even better - in performance of course.
However I would be grateful if someone can explain in easy language why it is better (or not) to include DDC module vs. "traditional" approach (with WM sound ICs) such as OVI40 UI PCB. I guess this kind of information would be good (and educational) for other forum followers as well.
Thank you in advance
Janez, S58J |
Title: Re:DDC Module2
Post by: DF8OE on 28. September 2020, 10:32:25
OVI40 UI can be used for direct sampling, too. My RF approach uses direct sampling, too.
You do not have- phase errors so no IQ-adjustment needed in TX and RX
- oscillator coupling to the output in TX
- to generate CW by DSP - you simply can generate a very clear output signal without hum or distortion
- spectrum/wf limits to 48KHz. Using OVI40 you will have 196KHz guaranteed, possibly 384KHz, too
- to use bandpass filters at all. Only lowpass filters for TX
Additionally full duplex is possible - following predistortion can be realized. Signal generating can be done without gaps down to a few KHz.
vy 73
Andreas
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Title: Re:DDC Module2
Post by: S58J on 28. September 2020, 12:13:52
Hi Andreas
Thank you for your quick reply. Just to be shure, when you list those bullets under "You do not have" you are talking about the simplicity/benefits of using OVI40 UI, am I right?
In terms of quality of each TRX I have two indicators: quality of RX and clean TX output. OK, the list goes on (frequency stability, filtering capabilities ...) but those two just listed are the major concerns for me.
If this DDC thread doesn't bring much to the table in the RX and TX area then we are coming back to the old philosophy: simpler is better. I'll stick to my OVI40 UI, hi.
Please take this as my own opinion, a person keen on HF contesting (high power), QRP operation (where I use only home made QRPs) and hunting DX on 50MHz. Others, more technical and development oriented persons, for shure might think differently.
Looking forward to your reply.
Janez, S58J |
Title: Re:DDC Module2
Post by: DF8OE on 28. September 2020, 12:44:44
OVI40 UI is just its name tells: it is an user interface. Today you can only add mcHF RF board which does not have good signal quality in TX and other restrictions / issues which are related to the RF signal processing.
Using a "DUC" (Direct up Converter) for TX and a "DDC" (Direct down Converter) for RX you do not need any mixing by analog signals. You directly digitalize incoming RF by a fast ADC and you get yor TX signal by direct producing it with a fast DAC. We already have had designed OVI40 to use this much more modern system. You only have to remove 4 100R resistors and add 4 wires to get direct connection from DUC/DDC to STM32 without walking through TX/RX audio codec.
Everything you already know (and hopefully love) on UHSDR will be present when running with DUC/DDC, too. But you get a much better signal quality, and if you want you can use your tube (or LDMOS) PA with >= 1KW without any doubts. For CW TX quality is universes better than from mixing concepts like mcHF.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: SP9BSL on 28. September 2020, 15:20:42
The DDC receiver is better
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Hi Artur,
There is something wrong with your receiver based on mcHF: the picture with -101dBm is at least 10dB higher than usual mcHF does, on the other side with DDC you show -133dBm which is too low. Did you calibrated the s-meter? |
Title: Re:DDC Module2
Post by: DD4WH on 28. September 2020, 17:31:46
Hi!
this looks like a very interesting development. However, I have not yet understood how/whether it can be used with existing OV I40 UI PCBs. Is this possible?
Or would it be better to build a Sparrow UI (is there anything called like this?) which has a possibility to plugin the DDC module?
Is there a place where I can read more about this project?
73 Frank DD4WH |
Title: Re:DDC Module2
Post by: SP9BSL on 28. September 2020, 19:19:35
For the Gain RX ->AUTO< setting (correct s-metr >0<), the DSP chip is as shown in the photo. OK?
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if you like then ok...
Leaving the codec gain to AUTO you add 24dB, sometimes less - it depends on AGC algorithm. In codec there is volume control but in fpga you haven't such thing. This is simple codec not a DSP.
A picture is better than thousand of words. The rx path is calibrated to S9 signal - as it should be, amplifier/attenuator are off and the shields are open. Antenna input left floating (same settings for both pictures): |
Title: Re:DDC Module2
Post by: DF8OE on 29. September 2020, 03:48:25
Hi Frank,
as I already wrote: no need to build a Sparrow. You can use OVI40 UI PCB for driving DUCDDC. Just inject I2S directly to STM32 by cutting the four resistors R8/R20/R26/R27 from audio codec and solder 4 wires there to connect to RF board. Output of DUCDDC behaves like the output of Audio codec and can be treated in software like this. But you do not have any of the disadvantages of mixing concept.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DD4WH on 29. September 2020, 08:39:40
Hi Andreas,
thanks for your explanations!
It is very hard for me to get an idea about this project, because there is virtually no information available (schematics, block diagram).
So, I understand that its still experimental and the DDC/DUC plugin does substitute the codec and the QSD and QSE.
Thanks again for the info!
73 Frank DD4WH |
Title: Re:DDC Module2
Post by: DF8OE on 29. September 2020, 15:05:25
There are noch schematics at this stage. But a schematic does not help for understanding - only for hardware bug-hunting... For understanding theory I attach a block diagrams
This is for RX |
Title: Re:DDC Module2
Post by: DF8OE on 29. September 2020, 15:11:57
...and this is for TX
Everything regarding I/Q processing is done on digital domain. Antenna is connected to an ADC in RX mode and to an DAC in TX mode. Data is feeded digital from a FPGA which does all the things QSD mixers and codec does.
I forgot:
In block diagram you see "Xilinx Core". Please replace this with FPGA core because of it is not fixed to Xilinx.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DD4WH on 29. September 2020, 17:05:52
Thanks Andreas, that really helps a lot to understand!
Best 73s,
Frank |
Title: Re:DDC Module2
Post by: DF8OE on 14. October 2020, 14:44:43
I think these "resistors" are non-linear because of inside the FPGA you find semiconducting things. So it is dependent on the voltage which the DMM uses for measuring. Best is to put DMM in diode test mode, connect positive pole to GND and check with negative pole if you can see protection diode on the recent pins.
vy 73
Andreas |
Title: Re:DDC Module2
Post by: Werner on 06. February 2021, 11:27:23
Hello Artur,
I am looking for a map of the assembly for the DDC Module 2.
(N7DDC DF-2020-USA)
I received the DDC Module 2 board from you.
Maybe jou can help me further?
I wish you a nice weekend and stay healthy!
vy73
Werner |
Title: Re:DDC Module2
Post by: Werner on 07. February 2021, 12:13:45
Hello Artur,
You helped me a lot with your very quick info !
That is the point of a good forum, thanks for your help !
I wish you a nice weekend and good health.
vy
Werner |
Title: Re:DDC Module2
Post by: DF8OE on 25. April 2021, 16:17:47
Hi Artur,
maybe you have swapped power values ::) ??
And DSP is both. I think you mean "mixing concept" instead of "DSP".
Stay healthy
vy 73
Andreas |
Title: Re:DDC Module2
Post by: DF8OE on 25. April 2021, 16:50:51
Hi Artur,
running devices "out-of-specs" is something that users who homebrew projects is standard for tens of years. But it is not without risk. I by myself use to follow the specs that are provided for an item.
Do not misunderstand:
There *are* constellations where I rely on the working of a device out of its specs.
But if there are speed grades for a device I have strong dought if it is a good idea to save some cent and rely that a device which is produced for a lower spped grade will work on x4 speed without following problems...
vy 73
Andreas |
Title: Re:DDC Module2
Post by: SP9BSL on 25. April 2021, 17:02:13
Hi,
different speed grade chips are produced on the same silicon wafer, the real diference (grade) is set by factory test and do/not meeting the required parameters for particular chip like noise, accidential failure etc, the chips grade often depends of placement on silicon wafer. This is official, who knows what chinese do doing their clones... |
Title: Re:DDC Module2
Post by: DF8OE on 25. April 2021, 17:07:58
Maybe in this case this is different. The chip housing is different. So not a speed test results in different classes - it is the production process itself.
But you have right: there are many and multiple things you have to check if you use a device out-of-specs. You get a better reliability if you have developed much more. It is an "instinct" that leads you ;D
vy 73
Andreas |
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