Title: about the maths in the FPGA
Post by: DF8OE on 17. May 2019, 11:10:48
Because of I will start with FPGA design "from the scratch" I want to learn much about the needs what must be processed inside FPGA.
I have looked at many web pages and tried to learn from as much as possible sources. I found a block diagram of RX FPGA processing on Pavel Denims "Red Pitaya Notes" GitHub:
Questions directed to the ones out who understand the maths in complete (Frank ;) ):
Of course we need complex multiplier and CIC decimation / filtering. After this stages I see three different decimation/FIR stages. It is not completely clear for me if these three stages are only neccessary because of we need a "broken integer" decimation (RP has 125MHz samplerate and decimation goes down to n*48KSPS) or if there are other reasons which dictate to use more than one FIR stage...
vy 73
Andreas |
Title: Re:about the maths in the FPGA
Post by: SP9BSL on 17. May 2019, 11:25:58
Hi Andreas,
the divided FIR filter is mainly because of less computation needed when we filter in multiple stages with wider bandwidth than in single, also the group delay is smaller because of shorter filter kernel.
Could you provide link to the place where the Red Pitaya algorithm is described? I do not see CORDIC implementation on the schematics you showed. |
Title: Re:about the maths in the FPGA
Post by: DF8OE on 17. May 2019, 11:31:14
Hi Slawek,
many informations are summarized in different places here (https://pavel-demin.github.io/red-pitaya-notes/).
EDIT:
Look also here (https://pavel-demin.github.io/red-pitaya-notes/sdr-receiver/).
vy 73
Andreas |
Title: Re:about the maths in the FPGA
Post by: SP9BSL on 17. May 2019, 11:44:37
Thank you Andreas,
with 125MHz sampling clock there is mismatch in decimated sample rate compared to "normal" audio sample rate, thus divided FIR filter acts as a sample rate converter which results in 48kHz data output instead of 50kHz what would be expected without this conversion. Therefore I use 122.88MHz sample clock to easy decimate to 48/96/192kHz. The rest is as you mention Frank's knowledge ;) |
Title: Re:about the maths in the FPGA
Post by: DF8OE on 17. May 2019, 11:56:35
Thanks Slawek. I use 76.8MHz sample rate (19.2*4). ADC is a 80MSPS type and very cheap. I use it twice... Running up to 38MHz I use one ADC, above 38MHz up to 75MHz I use two ADCs running at 180° clock. This is module1 (SW).
Module2 (VHF/UHF/SHF) uses AD9361 TRX chip running from 70MHz...6GHz.
vy 73
Andreas |
Title: Re:about the maths in the FPGA
Post by: DD4WH on 17. May 2019, 14:50:14
Hi Andres and Slawek,
well, I know merely nothing about FPGA and DDC radio . . . but I try to summarize some of my basic DSP experience here:
* the filters are only necessary because you need a good lowpass filter before a downsampling step [lowpass filter PLUS downsampling = decimation]
* the CIC does not have a nice frequency response, that is why a subsequent FIR compensation filter is often used (chapter 10.14 in Lyons 2011).
* as far as I know, the FIR decimation stages, but also the CIC decimation stages are divided into decimate-by-two stages, because it is much faster to decimate step-by-step --> see chapter 10.2 on multistage decimation in Lyons 2011
* maybe the use of polyphase CIC / FIR filters would be wise in order to save processor time (chapter 13.24 in Lyons 2011)
* or also halfband-FIR filters, but I have never used these yet
* my recommendation for further reading about these things would be:
Whiteley 2011 [CIC implementation etc.]
Lyons 2011 [absolute must for DSP !]
https://github.com/DD4WH/Teensy-ConvolutionSDR/wiki/Links-&-Resources (https://github.com/DD4WH/Teensy-ConvolutionSDR/wiki/Links-&-Resources)
But there are so many others that have written FPGA code for SDR, that it could save a lot of time to have a look into their code.
Best 73s
Frank |
Title: Re:about the maths in the FPGA
Post by: SP9BSL on 17. May 2019, 19:46:55
Hi Frank,
thanks for the answer, I agree: Lyons is the absolute basis, I have it of course, since 2001 (the first edition). After this book I recommend the marvelous free dspguide.com, and dspguru (mentioned in red pitaya notes).
@Andreas:
The ready code for ddc/duc conversion: I use the N2ADR code and recommend this for analysis (look at the N7DCC - D.Fainitski github pages in part related to module1 and Odyssey SDR). It has been written in Verilog.
The CORDIC algorithm FAQ: https://dspguru.com/dsp/faqs/cordic/ (https://dspguru.com/dsp/faqs/cordic/). |
Title: Re:about the maths in the FPGA
Post by: DF8OE on 18. May 2019, 07:43:28
Thanks for the input. Very good starting base ;D
vy 73
Andreas |
Title: Re:about the maths in the FPGA
Post by: DD4WH on 18. May 2019, 09:41:24
Hi Slawek,
thanks for the info! I never understood what CORDIC exactly is, but your link helped me to figure it out! Thanks!
73 Frank |
Title: Re:about the maths in the FPGA
Post by: DF8OE on 18. May 2019, 10:05:08
Designing a FPGA is somewhat a mixup of hardware understandings and software understandings. In principle you are designing a schematics within the FPGA using the available hardware resources "from the stock". The stock is not infinitely and you should design schematics by carefully select the parts for saving some which may be useful for other / additional tasks ::). It is an amazing thing.
I used much smaller parts in the 80th from Lattice (PALs and GALs). I designed them "by hand" using tools for my Atari ST. The amount of available hardware inside was so small that I can put connection using mouse and clicking in the complete shown inner schematics 8).
Now the "stock" is so big that this way is absolutely impossible but the FPGAs are very powerful...
vy 73
Andreas |
Diskussions- und Newsboard des DARC-Ortsverbandes I40 | Powered by YaBB SE
© 2001-2003, YaBB SE Dev Team. All Rights Reserved.
|